During testing of a device-under-test (DUT) using a number of test instruments, it is sometimes desirable to synchronize tasks on the various instruments so that the tasks are carried out at the same time. Examples of such tasks are those required for measuring the root-mean-square (RMS) power of a DUT in response to a stimulus signal, where a voltage measurement and a current measurement are made simultaneously and preferably at a known time. To make such a measurement in the prior art, a test system 2 in FIG. 1 is used. The test system 2 includes an LXI function generator 4 and two LXI digital multimeters (DMMs) 6, 8 connected to each either via a local area network (LAN) 10. Each of these instruments can accept downloaded user-specified application code and includes an IEEE 1588 clock that is synchronized with the other clocks in the test system using the IEEE 1588 time synchronization protocol. Discrepancies in the clocks in the different instruments can be reduced to less than 50 ns. All the instruments will be able to send time-stamped data to one another using peer-to-peer messages. Time-based triggers can also be set in these instruments. A time-based trigger is analogous to an alarm clock—it can be set to “go off” at a predetermined time. At that time, the instrument can be programmed to perform a specific function. This feature allows the different instruments in a test system to execute complex sequences of events autonomously, without intervention by a system controller. The use of time-based triggers requires the ability to schedule instrument actions in advance.
FIG. 2 is a general block diagram of a DMM 6, 8 in FIG. 1. The DMM includes a central processing unit (CPU) 12 and a measurement front-end 14 that is controlled by the CPU 12 to make a measurement. To obtain a power measurement, the function generator 4 generates a stimulus signal and sends a trigger message to the DMM 6, 8 triggering the DMM 6, 8 to make a measurement. When the DMM 6, 8 receives the trigger message for example at a time T1 as shown in FIG. 3, the CPU 12 executes a program in the DMM 6, 8 to parse and interpret the received trigger message. It is not until a short time later, at a time T2, that the CPU 12 is able to generate a trigger to the measurement front-end for it to make a measurement. Due to latency in the front-end 14 itself, the DMM 6, 8 actually makes the measurement at a time T3, which is a further time interval from the time T2. Thus, there is a delay within the DMM 6, 8 between receiving the trigger message and making the actual measurement. The propagation of the message through the network from the function generator to the DMM further adds to the delay between sending of the message by the function generator and making of the measurement by the DMM. However, as far as the function generator 4 is concerned, the DMM 6, 8 is expected to make the measurement when the message from the function generator 4 is received by the DMM 6, 8 at time T1. But due to both software and hardware latencies in the DMM 6, 8, the DMM 6, 8 is only able to make the measurement at time T3. The latency in the DMM 6, 8 is thus the time interval between time T3 and time T1. The latencies in the different DMMs 6, 8 in FIG. 1 and propagation delays in the network may cause the two DMMs 6, 8 to make respective measurements at different points in time although the trigger message is sent by the function generator 4 to both DMMs 6, 8 at the same time.
FIG. 4 shows a detailed block diagram of a DMM 6, 8 in FIG. 1. In addition to the CPU 12 and the measurement front-end 14, the DMM 6, 8 is now shown to include a IEEE 1588 clock 16, an execute time register 18 and a time comparator 20 for a different mode of operation. The sequence 30 of operations in the function generator 4 and the DMMs 6, 8 is next described with the aid of FIG. 5. To ensure that the DMMs 6, 8 make their respective measurements at the same point in time T3, the function generator 4 generates a stimulus signal and sends an event message to the two DMMs 6, 8 that includes a time T0 from which the DMMs 6, 8 obtain the time T3. This time T0 may be a time some event occurred or will take place in the function generator. When for example DMM1 4 receives the message at a time T1, the CPU 12 executes a program in DMM1 4 to parse and interpret the received message. The CPU 12 will modify the time T0 based on previously received instructions provided by a user to, for example, make a measurement precisely at a time T3 given by T0+TD, where TD is some application specific delay. A short time later, at a time T2, before the time T3, the CPU 12 loads the time T3 into the execute time register 18. The time comparator 20 compares the time in the execute time register 18 with the time from the IEEE 1588 clock 16. When the time in the execute time register 18 matches that of the IEEE 1588 clock 16, the comparator 20 sends a trigger to the measurement front-end 14 for it to make a measurement. Again due to latency in the front-end 14 itself, DMM1 6 actually makes the measurement at a time T4, which is a further time interval from the time T3. Thus, there is a still a latency in DMM1 6 between the time T4 and the time T3 even though the function generator 4 expects the measurement to be made at time T3. DMM2 8 may have a different latency resulting in the measurement being made at a time T5. Consequently, not only are the DMMs 6, 8 unable to make their respective measurements at the expected time T3, the DMMs 6, 8 might not be making their respective measurements at the same point in time.